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1 LT1725 general purpose isolated flyback controller november 2000 the lt ? 1725 is a monolithic switching regulator control- ler specifically designed for the isolated flyback topology. it drives the gate of an external mosfet and is generally powered from a third transformer winding. these features allow for an application input voltage limited only by external power path components. the third transformer winding also provides output voltage feedback informa- tion, such that an optoisolator is not required. its gate drive capability coupled with a suitable external mosfet can deliver load power up to tens of watts. the LT1725 has a number of features not found on other switching regulator ics presently available. by utilizing current mode switching techniques, it provides excellent ac and dc line regulation. its unique control circuitry can maintain regulation well into discontinuous mode in most applications. optional load compensation circuitry allows for improved load regulation. an optional undervoltage lockout pin halts operation when the application input voltage is too low. an optional external capacitor imple- ments a soft-start function. a 3v output is available at up to several ma for powering primary side application circuitry. n drives external power mosfet with external i sense resistor n application input voltage limited only by external power components n senses output voltage directly from primary side windingno optoisolator required n accurate regulation without user trims n regulation maintained well into discontinuous mode n switching frequency from 50khz to 250khz with external capacitor n available in 16-pin gn and so packages n optional load compensation n optional undervoltage lockout , ltc and lt are registered trademarks of linear technology corporation. n telecom isolated converters n offline isolated power supplies n instrumentation power supplies information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. final electrical specifications features descriptio u applicatio s u typical applicatio u 48v to iso 5v converter pgnd i sense gate v c fb r2 m1 irf610 220 h 74 h t1 10 h r13 v cc v in v in v out uvlo 3v out sgnd 1725 ta01 r cmpc r ocmp menab LT1725 r8 r7 c5 endly sfst oscap t on c3 r9 r1 r6 r4 3k r3 32.7k r10 v in r11 c1 c4 + c2 d1 d1n5820 d2 d1n4148 + c6
2 LT1725 (note 1) v cc supply voltage ................................................. 22v uvlo pin voltage .................................................... v cc i sense pin voltage .................................................... 2v fb pin current ..................................................... 2ma operating junction temperature range LT1725c ............................................... 0 c to 100 c LT1725i ........................................... C 40 c to 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number LT1725cgn LT1725cs LT1725ign LT1725is t jmax = 125 c, q ja = 110 c/w (gn) t jmax = 125 c, q ja = 100 c/w (so) package/order i for atio uu w absolute axi u rati gs w ww u top view s package 16-lead plastic so gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pgnd i sense sfst r ocmp r cmpc oscap v c fb gate v cc t on endly minenab sgnd uvlo 3v out the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 14v, gate open, v c = 1.4v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units power supply v cc v cc turn-on voltage l 14.0 15.1 16.0 v v cc hysteresis (v turn-on C v turn-off ) l 4.0 5.4 6.5 v i cc supply current l 61015ma start-up current l 120 280 m a feedback amplifier v fb feedback voltage 1.230 1.245 1.260 v l 1.220 1.270 v i fb feedback pin input current 500 na g m feedback amplifier transconductance d l c = 10 m a l 400 1000 1800 m mho i src , i snk feedback amplifier source or sink current l 30 50 80 m a v cl feedback amplifier clamp voltage 2.5 v reference voltage/current line regulation 12v v in 18v l 0.01 0.05 %/v voltage gain v c = 1v to 2v 2000 v/v soft-start charging current v sfst = 0v 25 40 50 m a soft-start discharge current v sfst = 1.5v, v uvlo = 0v 0.8 1.5 ma gate output v gate output high level i gate = 100ma l 11.5 12.1 v i gate = 500ma l 11.0 11.8 v output low level i gate = 100ma l 0.3 0.45 v i gate = 500ma l 0.6 1.0 v i gate output sink current in shutdown, v uvlo = 0v v gate = 2v l 1.2 2.5 ma t r rise time c l = 1000pf 30 ns t f fall time c l = 1000pf 30 ns consult factory for parts specified with wider operating temperature ranges. gn part marking 1725 1725i
3 LT1725 note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: component value range guaranteed by design. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 14v, gate open, v c = 1.4v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units current amplifier v c control pin threshold duty cycle = min 0.90 1.12 1.25 v l 0.80 1.35 v v isense switch current limit duty cycle 30% 220 250 270 mv duty cycle 30% l 200 280 mv duty cycle = 80% 220 mv d v isense / d v c 0.30 mv timing f switching frequency c oscap = 100pf 90 100 115 khz l 80 125 khz c oscap oscillator capacitor value (note 2) 33 200 pf t on minimum switch on time r ton = 50k 200 ns t ed flyback enable delay time r endly = 50k 200 ns t en minimum flyback enable time r menab = 50k 200 ns r t timing resistor value (note 2) 24 200 k w maximum switch duty cycle l 85 90 % load compensation sense offset voltage 25mv current gain factor 0.80 0.95 1.05 mv uvlo function v uvlo uvlo pin threshold l 1.21 1.25 1.29 v i uvlo uvlo pin bias current v uvlo = 1.2v C 0.25 + 0.1 + 0.25 m a v uvlo = 1.3v C 4.50 C 3.5 C 2.50 m a 3v output function v ref reference output voltage i load = 1ma l 2.8 3.0 3.2 v output impedance 10 w current limit l 815 ma uu u pi fu ctio s pgnd (pin 1): the power ground pin carries the gate node discharge current. this is typically a current spike of several hundred ma with a duration of tens of nanosec- onds. it should be connected directly to a good quality ground plane. i sense (pin 2): pin to measure switch current with exter- nal sense resistor. the sense resistor should be of a noninductive construction as high speed performance is essential. proper grounding technique is also required to avoid distortion of the high speed current waveform. a preset internal limit of nominally 250mv at this pin effects a switch current limit. sfst (pin 3): pin for optional external capacitor to effect soft-start function. see applications information for details.
4 LT1725 uu u pi fu ctio s r ocmp (pin 4): input pin for optional external load com- pensation resistor. use of this pin allows nominal com- pensation for nonzero output impedance in the power transformer secondary circuit, including secondary wind- ing impedance, output schottky diode impedance and output capacitor esr. in less demanding applications, this resistor is not needed. see applications information for more details. r cmpc (pin 5): pin for external filter capacitor for optional load compensation function. a common 0.1 m f ceramic capacitor will suffice for most applications. see applica- tions information for further details. oscap (pin 6): pin for external timing capacitor to set oscillator switching frequency. see applications informa- tion for details. v c (pin 7): this is the control voltage pin which is the output of the feedback amplifier and the input of the current comparator. frequency compensation of the overall loop is effected in most cases by placing a capaci- tor between this node and ground. fb (pin 8): input pin for external feedback resistor divider. the ratio of this divider, times the internal band- gap (v bg ) reference, times the effective output-to-third winding transformer turns ratio is the primary determi- nant of the output voltage. the thevenin equivalent resis- tance of the feedback divider should be roughly 3k. see applications information for more details. 3v out (pin 9): output pin for nominal 3v reference. this facilitates various user applications. this node is internally current limited for protection and is intended to drive either moderate capacitive loads of several hundred pf or less, or, very large capacitive loads of 0.1 m f or more. see applications information for more details. uvlo (pin 10): this pin allows the use of an optional external resistor divider to set an undervoltage lockout based upon v in (not v cc ) level. (note: if the v cc voltage is sufficient to allow the part to start up, but the uvlo pin is held below its threshold, output switching action will be disabled, but the part will draw its normal quiescent current from v cc . this typically causes a benign relaxation oscillation action on the v cc pin in the conventional trickle-charge bootstrapped configuration.) the bias current on this pin is a function of the state of the uvlo comparator; as the threshold is exceeded, the bias current increases. this creates a hysteresis band equal to the change in bias current times the thevenin impedance of the users resistive divider. the user may thereby adjust the impedance of the uvlo divider to achieve a desired degree of hysteresis. a 100pf capacitor to ground is recommended on this pin. see applications information for details. sgnd (pin 11): the signal ground pin is a clean ground. the internal reference, oscillator and feedback amplifier are referred to it. keep the ground path connection to the fb pin, oscap capacitor and the v c compensation capaci- tor free of large ground currents. minenab (pin 12): pin for external programming resistor to set minimum enable time. see applications information for details. endly (pin 13): pin for external programming resistor to set enable delay time. see applications information for details. t on (pin 14): pin for external programming resistor to set switch minimum on time. see applications information for details. v cc (pin 15): supply voltage for the LT1725. bypass this pin to ground with 1 m f or more. gate (pin 16): this is the gate drive to the external power mosfet switch and has large dynamic currents flowing through it. keep the trace to the mosfet as short as possible to minimize electromagnetic radiation and volt- age spikes. a series resistance of 5 w or more may help to dampen ringing in less than ideal layouts.
5 LT1725 block diagra w comp endly minenab t on i amp fdbk fb oscap osc mosfet driver uvlo v cc 3v out 3v reg (internal) bias v c soft-start load compensation i sense gate pgnd r ocmp sfst r cmpc sgnd 1725 bd logic
6 LT1725 ti i g diagra u ww v sw voltage v in gnd off on minimum t on enable delay minimum enable time 1725 td off on switch state flyback amp state 0.80 v flbk v flbk collapse detect enabled disabled disabled flyback error a plifier w + d1 t1 isolated v out c1 m1 + v in v c c2 r2 r1 fb v bg q1 q2 i i m i m i fxd enab 1725 ea
7 LT1725 the LT1725 is a current mode switcher controller ic designed specifically for the isolated flyback topology. the block diagram shows an overall view of the system. many of the blocks are similar to those found in traditional designs, including: internal bias regulator, oscillator, logic, current amplifier and comparator, driver and out- put switch. the novel sections include a special flyback error amplifier and a load compensation mechanism. also, due to the special dynamic requirements of flyback control, the logic system contains additional functionality not found in conventional designs. the LT1725 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier that derives its feedback informa- tion from the flyback pulse. due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. a good source of information on these topics is application note an19. error amplifierpseudo dc theory please refer to the simplified diagram of the flyback error amplifier. operation is as follows: when mosfet output switch m1 turns off, its drain voltage rises above the v in rail. the amplitude of this flyback pulse as seen on the third winding is given as: v v v i esr n flbk out f sec st = ++ () v f = d1 forward voltage i sec = transformer secondary current esr = total impedance of secondary circuit n st = transformer effective secondary-to-third winding turns ratio the flyback voltage is then scaled by external resistor divider r1/r2 and presented at the fb pin. this is then compared to the internal bandgap reference by the differ- ential transistor pair q1/q2. the collector current from q1 is mirrored around and subtracted from fixed current source i fxd at the v c pin. an external capacitor integrates this net current to provide the control voltage to set the current mode trip point. operatio u the relatively high gain in the overall loop will then cause the voltage at the fb pin to be nearly equal to the bandgap reference v bg . the relationship between v flbk and v bg may then be expressed as: v rr r v flbk bg = + () 12 2 combination with the previous v flbk expression yields an expression for v out in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: vv rr rn v i esr out bg st fsec = + () ? ? ? ? 12 2 1 additionally, it includes the effect of nonzero secondary output impedance, which is discussed below in further detail, see load compensation theory. the practical as- pects of applying this equation for v out are found in the applications information section. so far, this has been a pseudo-dc treatment of flyback error amplifier operation. but the flyback signal is a pulse, not a dc level. provision must be made to enable the flyback amplifier only when the flyback pulse is present. this is accomplished by the dotted line connections to the block labeled enab. timing signals are then required to enable and disable the flyback amplifier. error amplifierdynamic theory there are several timing signals which are required for proper LT1725 operation. please refer to the timing diagram. minimum output switch on time the LT1725 effects output voltage regulation via flyback pulse action. if the output switch is not turned on at all, there will be no flyback pulse and output voltage informa- tion is no longer available. this would cause irregular loop response and start-up/latchup problems. the solution cho- sen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. this in turn estab- lishes a minimum load requirement to maintain regula- tion. see applications information for further details.
8 LT1725 operatio u enable delay when the output switch shuts off, the flyback pulse appears. however, it takes a finite time until the trans- former primary side voltage waveform approximately rep- resents the output voltage. this is partly due to rise time on the mosfet drain node, but more importantly, due to transformer leakage inductance. the latter causes a volt- age spike on the primary side not directly related to output voltage. (some time is also required for internal settling of the feedback amplifier circuitry.) in order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turnoff command and the enabling of the feedback amplifier. this is termed enable delay. in certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. see applications information for further details. collapse detect once the feedback amplifier is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, which compares the flyback voltage (fb referred) to a fixed reference, nominally 80% of v bg . when the flyback waveform drops below this level, the feedback amplifier is disabled. this action accommodates both continuous and discontinuous mode operation. minimum enable time the feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed minimum enable time. this prevents lockup, especially when the output voltage is abnormally low, e.g., during start-up. the mini- mum enable time period ensures that the v c node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. the minimum enable time often determines the low load level at which output voltage regulation is lost. see applications information for details. effects of variable enable period it should now be clear that the flyback amplifier is enabled during only a portion of the cycle time. this can vary from the fixed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of flyback amp behavior will then be directly affected by the variable enable period. these include effective transconductance and v c node slew rate. load compensation theory the LT1725 uses the flyback pulse to obtain information about the isolated output voltage. a potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, t1 m1 r3 50k v in r2 load comp i r1 fb v bg q1 q2 i m i m r ocmp r cmpc r sense i sense 1725 f01 q3 + a1 figure 1. load compensation diagram
9 LT1725 transformer secondary and output capacitor. this has been represented previously by the expression i sec ? esr. however, it is generally more useful to convert this expression to an effective output impedance. because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the off duty cycle. that is: r esr dc out off = ? ? ? ? 1 where r out = effective supply output impedance esr = lumped secondary impedance dc off = off duty cycle expressing this in terms of the on duty cycle, remember- ing dc off = 1 C dc, r esr dc out = ? ? ? ? 1 1 dc = on duty cycle in less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external fb resistor divider adjusted to compensate for nominal expected error. in more demanding applications, output impedance error may be minimized by the use of the load compensa- tion function. to implement the load compensation function, a voltage is developed that is proportional to average output switch current. this voltage is then impressed across the external r ocmp resistor, and the resulting current acts to increase the v bg reference used by the flyback error amplifier. as output loading increases, average switch current increases to maintain rough output voltage regulation. this causes an increase in r ocmp resistor current which effects a corresponding increase in target output voltage. assuming a relatively fixed power supply efficiency, eff, power out = eff ? power in v out ? i out = eff ? v in ? i in average primary side current may be expressed in terms of output current as follows: operatio u i v v eff i in out in out = ? ? ? ? combining the efficiency and voltage terms in a single variable: i in = k1 ? i out , where k v v eff out in 1 = ? ? ? ? switch current is converted to voltage by the external sense resistor and averaged/lowpass filtered by r3 and the external capacitor on r cmpc . this voltage is then impressed across the external r ocmp resistor by op amp a1 and transistor q3. this produces a current at the collector of q3 which is then mirrored around and then subtracted from the fb node. this action effectively in- creases the voltage required at the top of the r1/r2 feedback divider to achieve equilibrium. so the effective change in v out target is: d=d () ? ? ? ? d d = ? ? ? ? vki r r rror v i k r r rr out out sense ocmp out out sense ocmp 112 112 (||) ( || ) nominal output impedance cancellation is obtained by equating this expression with r out : rk r r r r and rk r r r r where out sense ocmp ocmp sense out = ? ? ? ? = ? ? ? ? 112 112 ( || ) ( || ) k1 = dimensionless variable related to v in , v out and efficiency as above r sense = external sense resistor r out = uncompensated output impedance (r1||r2) = impedance of r1 and r2 in parallel the practical aspects of applying this equation to deter- mine an appropriate value for the r ocmp resistor are found in the applications information section.
10 LT1725 applicatio s i for atio wu uu transformer design considerations transformer specification and design is perhaps the most critical part of applying the LT1725 successfully. in addi- tion to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful. turns ratios note that due to the use of the external feedback resistor divider ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given application. in other words, screwball turns ratios like 1.736:1.0 can scrupulously be avoided! in contrast, simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and mutual inductance. turns ratio can then be chosen on the basis of desired duty cycle. however, remember that the input supply voltage plus the second- ary-to-primary referred version of the flyback pulse (in- cluding leakage spike) must not exceed the allowed external mosfet breakdown rating. leakage inductance transformer leakage inductance (on either the primary or secondary) causes a spike after output switch turnoff. this is increasingly prominent at higher load currents, where more stored energy must be dissipated. in many cases a snubber circuit will be required to avoid overvoltage breakdown at the output switch node. application note an19 is a good reference on snubber design. in situations where the flyback pulse extends beyond the enable delay time, the output voltage regulation will be affected to some degree. it is important to realize that the feedback system has a deliberately limited input range, roughly 50mv referred to the fb node, and this works to the users advantage in rejecting large, i.e., higher voltage, leakage spikes. in other words, once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. so the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible, observing mosfet breakdown, such that leakage spike duration is as short as possible. as a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to perhaps ten percent cause increasing regulation error. severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current. this curious condition potentially occurs when the leak- age spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this will typically reduce the output volt- age abruptly to a fraction, perhaps between one-third to two-thirds of its correct value. if load current is reduced sufficiently, the system will snap back to normal opera- tion. when using transformers with considerable leakage inductance, it is important to exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at a abnormally low value, the system has a problem. this will usually be evident by simultaneously monitoring the v sw waveform on an oscilloscope to observe leakage spike behavior firsthand. a final notethe susceptibility of the system to bistable behavior is somewhat a function of the load i/v characteristics. a load with resistive, i.e., i = v/r behavior is the most susceptible to bistability. loads which exhibit cmossy, i.e., i = v 2 /r behavior are less susceptible. secondary leakage inductance in addition to the previously described effects of leakage inductance in general, leakage inductance on the second- ary in particular exhibits an additional phenomenon. it forms an inductive divider on the transformer secondary,
11 LT1725 applicatio s i for atio wu uu which reduces the size of the primary-referred flyback pulse used for feedback. this will increase the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomena is load indepen- dent. to the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the feedback resistor divider ratio. winding resistance effects resistance in either the primary or secondary will act to reduce overall efficiency (p out /p in ). resistance in the secondary increases effective output impedance which degrades load regulation, (at least before load compensa- tion is employed). bifilar winding a bifilar or similar winding technique is a good way to minimize troublesome leakage inductances. however re- member that this will increase primary-to-secondary ca- pacitance and limit the primary-to-secondary breakdown voltage, so bifilar winding is not always practical. finally, the ltc applications group is available to assist in the choice and/or design of the transformer. happy winding! selecting feedback resistor divider values the expression for v out developed in the operation sec- tion can be rearranged to yield the following expression for the r1/r2 ratio: rr r v v i esr v n out f sec bg st 12 2 + () = ++ () where: v out = desired output voltage v f = switching diode forward voltage i sec ? esr = secondary resistive losses v bg = data sheet reference voltage value n st = effective secondary-to-third winding turns ratio the above equation defines only the ratio of r1 to r2, not their individual values. however, a second equation for two unknowns is obtained from noting that the thevenin impedance of the resistor divider should be roughly 3k for bias current cancellation and other reasons. selecting r ocmp resistor value the operation section previously derived the following expressions for r out , i.e., effective output impedance and r ocmp , the external resistor value required for its nominal compensation: r esr dc rk r r rr out ocmp sense out = ? ? ? ? = ? ? ? ? () 1 1 112 || while the value for r ocmp may therefore be theoretically determined, it is usually better in practice to employ empirical methods. this is because several of the required input variables are difficult to estimate precisely. for instance, the esr term above includes that of the trans- former secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resis- tance. similarly, k1 appears to be a simple ratio of v in to v out times (differential) efficiency, but theoretically esti- mating efficiency is not a simple calculation. the sug- gested empirical method is as follows: build a prototype of the desired supply using the eventual secondary components. temporarily ground the r cmpc pin to disable the load compensation function. operate the supply over the expected range of output current loading while measuring the output voltage deviation. approxi- mate this variation as a single value of r out (straight line approximation). calculate a value for the k1 constant based on v in , v out and the measured (differential) effi- ciency. these are then combined with r sense as indicated to yield a value for r ocmp . verify this result by connecting a resistor of roughly this value from the r ocmp pin to ground. (disconnect the ground short to r cmpc and connect the requisite 0.1 m f filter capacitor to ground.) measure the output impedance
12 LT1725 with the new compensation in place. modify the original r ocmp value if necessary to increase or decrease the effective compensation. selecting oscillator capacitor value the switching frequency of the LT1725 is set by an external capacitor connected between the oscap pin and ground. recommended values are between 200pf and 33pf, yielding switching frequencies between 50khz and 250khz. figure 2 shows the nominal relationship between external capacitance and switching frequency. to mini- mize stray capacitance and potential noise pickup, this capacitor should be placed as close as possible to the ic and the oscap node length/area minimized. applicatio s i for atio wu uu minimum on time this time defines a period whereby the normal switch current limit is ignored. this feature provides immunity to the leading edge current spike often seen at the source node of the external power mosfet, due to rapid charging of its gate/source capacitance. this current spike is not indicative of actual current level in the transformer pri- mary, and may cause irregular current mode switching action, especially at light load. however, the user must remember that the LT1725 does not skip cycles at light loads. therefore, minimum on time will set a limit on minimum delivered power and con- sequently a minimum load requirement to maintain regu- lation (see minimum load considerations). similarly, minimum on time has a direct effect on short-circuit be- havior (see maximum load/short-circuit considerations). the user is normally tempted to set the minimum on time to be short to minimize these load related consequences. (after all, a smaller minimum on time approaches the ideal case of zero, or no minimum.) however, a longer time may be required in certain applications based on mosfet switching current spike considerations. enable delay time this function provides a programmed delay between turnoff of the gate drive node and the subsequent enabling of the feedback amplifier. at high loads, a primary side voltage spike after mosfet turnoff may be observed due c oscap (pf) 30 50 f osc (khz) 100 200 300 100 200 1725 f02 figure 2. f osc vs oscap value selecting timing resistor values there are three internal one-shot times that are pro- grammed by external application resistors: minimum on time, enable delay time and minimum enable time. these are all part of the isolated flyback control technique, and their functions have been previously outlined in the theory of operation section. figures 3 shows nominal observed time versus external resistor value for these functions. the following information should help in selecting and/or optimizing these timing values. r t (k ) 20 100 500 time (ns) 1000 100 250 1725 f03 figure 3. one shot times vs programming resistor
13 LT1725 to transformer leakage inductance. this spike is not in- dicative of actual output voltage (see figure 4b). delaying the enabling of the feedback amplifier allows this system to effectively ignore most or all of the voltage spike and maintain proper output voltage regulation. the enable delay time should therefore be set to the maximum ex- pected duration of the leakage spike. this may have implications regarding output voltage regulation at mini- mum load (see minimum load considerations). a second benefit of the enable delay time function occurs at light load. under such conditions the amount of energy stored in the transformer is small. the flyback waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage (see figure 4c). so the enable delay time should also be set long enough to ignore the irrelevant portion of the flyback waveform at light load. additionally, there are cases wherein the gate output is called upon to drive a large geometry mosfet such that the turnoff transition is slowed significantly. under such circumstances, the enable delay time may be increased to accommodate for the lengthy transition. minimum enable time this function sets a minimum duration for the expected flyback pulse. its primary purpose is to provide a mini- mum source current at the v c node to avoid start-up problems. average start-up v c current = minimum enable time switching frequency i src minimum enable time can also have implications at light load (see minimum load considerations). the temptation is to set the minimum enable time to be fairly short, as this is the least restrictive in terms of minimum load behavior. however, to provide a reliable minimum start-up current of say, nominally 1 m a, the user should set the minimum enable time at no less that 2% of the switching period (= 1/switching frequency). current sense resistor considerations the external current sense resistor allows the user to optimize the current limit behavior for the particular appli- cation under consideration. as the current sense resistor is varied from several ohms down to tens of milliohms, peak switch current goes from a fraction of an ampere to tens of amperes. care must be taken to ensure proper circuit operation, especially with small current sense resistor values. for example, a peak switch current of 10a requires a sense resistor of 0.025 w . note that the instantaneous peak power in the sense resistor is 2.5w, and it must be rated accord- ingly. the LT1725 has only a single sense line to this re- sistor. therefore, any parasitic resistance in the ground side connection of the sense resistor will increase its apparent value. in the case of a 0.025 w sense resistor, one milliohm of parasitic resistance will cause a 4% reduction in peak switch current. so resistance of printed circuit copper traces and vias cannot necessarily be ignored. an additional consideration is parasitic inductance. induc- tance in series with the current sense resistor will accen- tuate the high frequency components of the current waveform. in particular, the gate switching spike and multimegahertz ringing at the mosfet can be considerably applicatio s i for atio wu uu enable delay time needed 1725 f04 discontinuous mode ringing idealized flyback waveform mosfet gate drive flyback waveform with large leakage spike at heavy load ?low?flyback waveform at light load b a c enable delay time needed figure 4
14 LT1725 amplified. if severe enough, this can cause erratic opera- tion. for example, assume 3nh of parasitic inductance (equivalent to about 0.1 inch of wire in free space) is in series with an ideal 0.025 w sense resistor. a zero will be formed at f = r/(2 p l), or 1.3mhz. above this frequency the sense resistor will behave like an inductor. several techniques can be used to tame this potential parasitic inductance problem. first, any resistor used for current sensing purposes must be of an inherently non- inductive construction. mounting this resistor directly above an unbroken ground plane and minimizing its ground side connection will serve to absolutely minimize parasitic inductance. in the case of low valued sense resistors, these may be implemented as a parallel combi- nation of several resistors for the thermal considerations cited above. the parallel combination will help to lower the parasitic inductance. finally, it may be necessary to place a pole between the current sense resistor and the LT1725 i sense pin to undo the action of the inductive zero (see figure 5). a value of 51 w is suggested for the resistor, while the capacitor is selected empirically for the particular application and layout. using good high frequency mea- surement techniques, the i sense pin waveform may be observed directly with an oscilloscope while the capacitor value is varied. applicatio s i for atio wu uu gate parasitic inductance c comp r sense l p 1725 f05 51 pgnd sgnd i sense f = r sense 2 l p sense resistor zero at: f = 1 2 (51 )c comp compensating pole at: c comp = l p r sense (51 ) for cancellation: figure 5 soft-start function the LT1725 contains an optional soft-start function that is enabled by connecting an explicit external capacitor be- tween the sfst pin and ground. internal circuitry prevents the control voltage at the v c pin from exceeding that on the sfst pin. the soft-start function is enagaged whenever v cc power is removed, or as a result of either undervoltage lockout or thermal (overtemperature) shutdown. the sfst node is then discharged to roughly a v be above ground. (remember that the v c pin control node switching thresh- old is deliberately set at a v be plus several hundred millivolts.) when this condition is removed, a nominal 40 m a current acts to charge up the sfst node towards roughly 3v. so, for example, a 0.1 m f soft-start capacitor will place a 0.4v/ms limit on the ramp rate at the v c node. uvlo pin function the uvlo pin effects an undervoltage lockout function with at threshold of roughly 1.25v. an external resistor divider between the input supply and ground can then be used to achieve a user-programmable undervoltage lock- out (see figure 6a). an additional feature of this pin is that there is a change in the input bias current at this pin as a function of the state of the internal uvlo comparator. as the pin is brought above the uvlo threshold, the bias current sourced by the part increases. this positive feedback effects a hysteresis band for reliable switching action. note that the size of the hysteresis is proportional to the thevenin impedance of the external uvlo resistor divider network, which makes it user programmable. as a rough rule of thumb, each 4k or so of impedance generates about 1% of hysteresis. (this is based on roughly 1.25v for the threshold and 3 m a for the bias current shift.) even in good quality ground plane layouts, it is common for the switching node (mosfet drain) to couple to the uvlo pin with a stray capacitance of several thousandths of a pf. to ensure proper uvlo action, a 100pf capacitor is recommended from this pin to ground as shown in figure 6b. this will typically reduce the coupled noise to a few millivolts. the uvlo filter capacitor should not be made much larger than a few hundred pf, however, as the hysteresis action will become too slow. in cases where further filtering is required, e.g., to attenuate high speed supply ripple, the topology in figure 6c is recommended. resistor r1 has been split into two equal parts. this provides a node for effecting capacitor filtering of high
15 LT1725 v in (6a) ?tandard?uvlo divider topology uvlo r1 r2 v in (6b) filter capacitor directly on uvlo node uvlo r1 r2 c1 100pf v in (6c) recommended topology to filter high frequency ripple uvlo r1/2 r1/2 r2 1725 f06 c2 c1 100pf applicatio s i for atio wu uu figure 6 speed supply ripple, while leaving the uvlo pin node impedance relatively unchanged at high frequency. internal wide hysteresis undervoltage lockout the LT1725 is designed to implement isolated dc/dc converters operating from input voltages of typically 48v or more. the standard operating topology utilizes a third transformer winding on the primary side that provides both feedback information and local power for the LT1725 via its v cc pin. however, this arrangement is not inherently self-starting. start-up is effected by the use of an external trickle-charge resistor and the presence of an internal wide hysteresis undervoltage lockout circuit that monitors v cc pin voltage (see figure 7). operation is as follows: trickle charge resistor r1 is connected to v in and supplies a small current, typically on the order of a single ma, to charge c1. at first, the LT1725 is off and draws only its start-up current. after some time, the voltage on c1 (v cc ) reaches the v cc turn-on threshold. the LT1725 then turns on abruptly and draws its normal supply current. switching action commences at the gate pin and the mosfet begins to deliver power. the voltage on c1 begins to decline as the LT1725 draws its normal supply current, which greatly exceeds that delivered by r1. after some time, typically tens of milliseconds, the output voltage approaches its desired value. by this time, the third transformer winding is providing virtually all the supply current required by the LT1725. one potential design pitfall is undersizing the value of capacitor c1. in this case, the normal supply current + v cc i vcc 1725 f07 r1 c1 v in v in LT1725 gate pgnd sgnd i vcc v vcc v on threshold 0 v gate figure 7 drawn by the LT1725 will discharge c1 too rapidly; before the third winding drive becomes effective, the v cc turn-off threshold will be reached. the LT1725 turns off, and the v cc node begins to charge via r1 back up to the turn-on threshold. depending upon the particular situation, this may result in either several on-off cycles before proper operation is reached, or, permanent relaxation oscillation at the v cc node. component selection is as follows: resistor r1 should be selected to yield a worst-case minimum charging current greater than the maximum rated LT1725 start-up current, and a worst-case maxi- mum charging current less than the minimum rated LT1725 supply current.
16 LT1725 capacitor c1 should then be made large enough to avoid the relaxation oscillatory behavior described above. this is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. empirical testing is recommended. (use of the optional soft-start function will lengthen the power-up timing and require a correspondingly larger value for c1.) a further notecertain users may wish to utilize the general functionality of the LT1725, but may have an available input voltage significantly lower than, say, 48v. if this input voltage is within the allowable v cc range, i.e., perhaps 20v maximum, the internal wide hysteresis range uvlo function becomes counterproductive. in such cases it is simply better to operate the LT1725 directly from the available dc input supply. the lt1737 is identical to the LT1725, with the exception that it lacks the internal wide hysteresis uvlo function. it is therefore designed to operate directly from dc input supplies in the range of 4.5v to 20v. see the lt1737 data sheet for further information. frequency compensation loop frequency compensation is performed by connect- ing a capacitor from the output of the error amplifier (v c pin) to ground. an additional series resistor, often re- quired in traditional current mode switcher controllers, is usually not required and can even prove detrimental. the phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a zero to the loop response. in further contrast to traditional current mode switchers, v c pin ripple is generally not an issue with the LT1725. the dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the v c voltage changes during the flyback pulse, but is then held during the subsequent switch on portion of the next cycle. this action naturally holds the v c voltage stable during the current comparator sense action (current mode switching). output voltage error sources conventional nonisolated switching power supply ics typically have only two substantial sources of output voltage error: the internal or external resistor divider network that connects to v out and the internal ic refer- ence. the LT1725, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. here is a list of possible error sources and their effective contribution. internal voltage reference the internal bandgap voltage reference is, of course, imperfect. its error, both at 25 c and over temperature is already included in the specifications. user programming resistors output voltage is controlled by the user-supplied feedback resistor divider ratio. to the extent that the resistor ratio differs from the ideal value, the output voltage will be proportionally affected. highest accuracy systems will demand 1% components. schottky diode drop the LT1725 senses the output voltage from the trans- former primary side during the flyback portion of the cycle. this sensed voltage therefore includes the forward drop, v f , of the rectifier (usually a schottky diode). the nominal v f of this diode should therefore be included in feedback resistor divider calculations. lot to lot and ambient tem- perature variations will show up as output voltage shift/ drift. secondary leakage inductance leakage inductance on the transformer secondary re- duces the effective secondary-to-third winding turns ratio (n s /n t ) from its ideal value. this will increase the output voltage target by a similar percentage. to the extent that secondary leakage inductance is constant from part to part, this can be accommodated by adjusting the feedback resistor ratio. applicatio s i for atio wu uu
17 LT1725 output impedance error an additional error source is caused by transformer sec- ondary current flow through the real life nonzero imped- ances of the output rectifier, transformer secondary and output capacitor. because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the dc lumped secondary impedance times the inverse of the off duty cycle. if the output load current remains relatively constant, or, in less critical applications, the error may be judged acceptable and the feedback resistor divider ratio adjusted for nomi- nal expected error. in more demanding applications, out- put impedance error may be minimized by the use of the load compensation function (see load compensation). minimum load considerations the LT1725 generally provides better low load perfor- mance than previous generation switcher/controllers uti- lizing indirect output voltage sensing techniques. specifically, it contains circuitry to detect flyback pulse collapse, thereby supporting operation well into discon- tinuous mode. nevertheless, there still remain constraints to ultimate low load operation. these relate to the mini- mum switch on time and the minimum enable time. discontinuous mode operation will be assumed in the following theoretical derivations. as outlined in the operation section, the LT1725 utilizes a minimum output switch on time, t on . this value can be combined with expected v in and switching frequency to yield an expression for minimum delivered power. minimum power f l vt vi pri in on out out = ? ? ? ? () = 1 2 2 this expression then yields a minimum output current constraint: i f lv vt out min pri out in on () = ? ? ? ? () 1 2 2 where f = switching frequency l pri = transformer primary side inductance v in = input voltage v out = output voltage t on = output switch minimum on time an additional constraint has to do with the minimum enable time. the LT1725 derives its output voltage infor- mation from the flyback pulse. if the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. the onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, t ed , plus the minimum enable time, t en . minimum power delivered to the load is then: minimum power f l vtt vi sec out en ed out out = ? ? ? ? + () [] = 1 2 2 which yields a minimum output constraint: i fv l tt out min out sec ed en () = ? ? ? ? + () 1 2 2 where f = switching frequency l sec = transformer secondary side inductance v out = output voltage t ed = enable delay time t en = minimum enable time note that generally, depending on the particulars of input and output voltages and transformer inductance, one of the above constraints will prove more restrictive. in other words, the minimum load current in a particular applica- tion will be either output switch minimum on time constrained, or minimum flyback pulse time constrained. (a final notel pri and l sec refer to transformer induc- tance as seen from the primary or secondary side respec- tively. this general treatment allows these expressions to be used when the transformer turns ratio is nonunity.) applicatio s i for atio wu uu
18 LT1725 applicatio s i for atio wu uu maximum load/short-circuit considerations the LT1725 is a current mode controller. it uses the v c node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. the internal clamp on the v c node, nominally 2.5v, then acts as an output switch peak current limit. this 2.5v at the v c pin corresponds to a value of 250mv at the i sense pin, when the (on) switch duty cycle is less than 40%. for a duty cycle above 40%, the internal slope compensation mechanism lowers the effective i sense voltage limit. for example, at a duty cycle of 80%, the nominal i sense voltage limit is 220mv. this action be- comes the switch current limit specification. maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. overcurrent conditions are handled by the same mecha- nism. the output switch turns on, the peak current is quickly reached and the switch is turned off. because the output switch is only on for a small fraction of the available period, power dissipation is controlled. loss of current limit is possible under certain conditions. remember that the LT1725 normally exhibits a minimum switch on time, irrespective of current trip point. if the duty cycle exhibited by this minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current will not be controlled at the nominal value, and will cycle-by-cycle ratchet up to some higher level. expressed mathemati- cally, the requirement to maintain short-circuit control is: tf vi r vn on f sc sec in sp < + () where t on = output switch minimum on time f = switching frequency i sc = short-circuit output current v f = output diode forward voltage at i sc r sec = resistance of transformer secondary v in = input voltage n sp = secondary-to-primary turns ratio ( n sec /n pri ) trouble is typically only encountered in applications with a relatively high product of input voltage times secondary- to-primary turns ratio and/or a relatively long minimum switch on time. (additionally, several real world effects such as transformer leakage inductance, ac winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate.) thermal considerations care should be taken to ensure that the worst-case input voltage condition does not cause excessive die tempera- tures. the 16-lead so package is rated at 100 c/w, and the 16-lead gn at 110 c/w. average supply current is simply the sum of quiescent current given in the specifications section plus gate drive current. gate drive current can be computed as: i g = f ? q g where q g = total gate charge f = switching frequency (note: total gate charge is more complicated than c gs ? v g as it is frequently dominated by miller effect of the c gd . furthermore, both capacitances are nonlinear in practice. fortunately, most mosfet data sheets provide figures and graphs which yield the total gate charge directly per operating conditions.) nearly all gate drive power is dissi- pated in the ic, except for a small amount in the external gate series resistor, so total ic dissipation may be com- puted as: p d(total) = v cc (i q + ? f ? q g ), where i q = quiescent current (from specifications) q g = total gate charge f = switching frequency v cc = LT1725 supply voltage
19 LT1725 switch node considerations for maximum efficiency, gate drive rise and fall times are made as short as practical. to prevent radiation and high frequency resonance problems, proper layout of the components connected to the ic is essential, especially the power paths (primary and secondary). b field (mag- netic) radiation is minimized by keeping mosfet leads, output diode, and output bypass capacitor leads as short as possible. e field radiation is kept low by minimizing the length and area of all similar traces. a ground plane should always be used under the switcher circuitry to prevent interplane coupling. the high speed switching current paths are shown sche- matically in figure 8. minimum lead length in these paths are essential to ensure clean switching and minimal emi. the path containing the input capacitor, transformer pri- mary and mosfet, and the path containing the trans- former secondary, output diode and output capacitor contain nanosecond rise and fall times. keep these paths as short as possible. applicatio s i for atio wu uu gate drive resistor considerations the gate drive circuitry internal to the LT1725 has been designed to have as low an output impedance as practi- cally possibleonly a few ohms. a strong l/c resonance is potentially presented by the inductance of the path leading to the gate of the power mosfet and its overall gate capacitance. for this reason the path from the gate package pin to the physical mosfet gate should be kept as short as possible, and good layout/ground plane prac- tice used to minimize the parasitic inductance. an explicit series gate drive resistor may be useful in some applications to damp out this potential l/c resonance (typically tens of mhz). a minimum value of perhaps several ohms is suggested, and higher values (typically a few tens of ohms) will offer increased damping. however, as this resistor value becomes too large, gate voltage rise time will increase to unacceptable levels, and efficiency will suffer due to the sluggish switching action. figure 8. high speed current switching paths + + pgnd gate 1725 f08 gate discharge path primary power path secondary power path v cc v cc v in +
20 LT1725 typical applicatio s u figure 9. 48v to isolated 15v converter pgnd i sense gate v c fb r2 0.1 m1 irf620 t1 vp5-0155 r12 5.1 v cc v out 15v uvlo 3v out sgnd 1725 f09a r cmpc r ocmp menab LT1725 r7 51k r6 51k c7 47pf 6314 10 9 8 7 13 12 4 5 15 11 1 2 16 endly sfst oscap t on c6 1nf r8 6.2k r11 150 d3 1n5257 d4 1n5257 d2 mbrs1100 r10 18 v in r1 24k c1 22 f r14 820k r15 33k r9 51 r5 51k r4 3.01k 1% r3 34.0k 1% c8 0.1 f + c4 150 f d1 mbrd660 d5 bas16 + c9 470pf c3 100pf c2 1.5 f 3 8 5 9 4 1 12 2 11 10 3 6 7 c5 1 f r13 750 1w c10 100pf versa-pak is a trademark of coiltronics, inc telecom 48v to isolated 15v application the design in figure 9 accepts an input voltage in the range of 36v to 72v and outputs an isolated 15v at up to 2a. transformer t1 is an off-the-shelf versa-pak tm #vp5-0155, produced by coiltronics. as manufactured, it consists of six ideally identical independent windings. in this application, three windings are stacked in series on the primary side and two are placed in parallel on the secondary side. this arrangement provides a 3:1 primary- to-secondary turns ratio while maximizing overall effi- ciency. the remaining winding provides a primary-side ground-referred version of the flyback voltage waveform for both feedback information and providing power to the LT1725 itself. capacitor c7 sets the switching frequency at approxi- mately 200khz. optimal load compensation for the trans- former and secondary circuit components is set by resistor r8. output voltage regulation and overall efficiency are shown in the accompanying graphs. the resistor divider formed by r14 and r15 sets the undervoltage lockout threshold at about 32v, with a hysteresis band of about 2v. the soft-start and 3v out features are unused as shown.
21 LT1725 typical applicatio s u i load (a) 0 v out (v) 15.0 2.0 1725 f09b 14.5 0.5 1.0 1.5 2.5 15.5 v in = 36v v in = 72v v in = 48v application regulation application efficiency i load (a) 0.01 60 efficiency (%) 70 80 90 0.1 1 10 1725 f09c 50 40 30 20 v in = 48v v out = 15v 48v to isolated 15v application parts list t1: coiltronics vp5-0155 versa-pak m1: international rectifier irf620. 200v, 0.8 w n-channel mosfet d1: motorola mbrd660. 6a, 60v schottky diode d2: motorola mbrs1100. 1a, 100v schottky diode d3, d4: 1n5257. 33v, 500mw zener diode d5: bas16. 75v rectifier diode c1: avx tpsd226m025r0200. 22 m f, 25v tantalum capacitor c2a, c2b, c2c: vishay/vitramon vj1825y155mxb. 1.5 m f, 100v x7r ceramic capacitor c3: 100pf, 100v, x7r ceramic capacitor c4: sanyo 20sv150m. 150 m f, 20v, os-con electrolytic capacitor c5: 1 m f, 25v, z5u ceramic capacitor c6: 1nf, 25v, x7r ceramic capacitor c7: 47pf, 25v npo/cog ceramic capacitor c8: 0.1 m f, 25v, z5u ceramic capacitor c9: 470pf, 25v, x7r ceramic capacitor c10: 100pf, 25v, x7r ceramic capacitor r1: 24k, 1/4w, 5% resistor r2: irc lr2010. 0.1 w , 1/2w current sense resistor r3: 34.0k, 1% resistor r4: 3.01k, 1% resistor r5, r6, r7: 51k, 5% resistor r8: 6.2k, 5% resistor r9: 51 w , 5% resistor r10: 18 w , 5% resistor r11: 150 w , 1/4w, 5% resistor r12: 5.1 w , 5% resistor r13a, r13b: 1.5k, 1/2w, 5% resistor r14: 820k, 5% resistor r15: 33k, 5% resistor
22 LT1725 typical applicatio s u telecom 48v to isolated 5v application the design in figure 10 accepts an input voltage in the range of 36v to 72v and outputs an isolated 5v at up to 2a. transformer t1 is available as a coiltronics ctx02-14989. capacitor c7 sets the switching frequency at approxi- mately 275khz. optimal load compensation for the trans- former and secondary circuit components is set by resistor r8. output voltage regulation and overall efficiency are shown in the accompanying graphs. efficiency is shown both with and without the r11 preload. the resistor divider formed by r13 and r14 sets the undervoltage lockout threshold at about 32v, with a hysteresis band of about 2v. the soft-start and 3v out features are unused as shown. pgnd i sense gate v c fb r2 0.18 m1 irf620 t1 ctx02-14989 v cc v out 5v uvlo 3v out sgnd 1725 f10a r cmpc r ocmp menab LT1725 r7 51k r6 51k c7 47pf 6314 10 9 8 7 13 12 4 5 15 11 1 2 16 endly sfst oscap t on c6 1nf r8 2.7k r12 68 r1 47k v in r10 22 r13 820k r14 33k r5 51k r4 3.01k 1% r3 35.7k 1% c8 0.1 f + c3 150 f d1 12cwq06 r9 18 c5 470pf d2 bas16 + c4 150pf c2 1.5 f c1 15 f 4 2 11 9 12 10 1 6 r11 51 1w c9 100pf c10 1 f figure 10. 48v to isolated 5v converter i load (a) 0 v out (v) 5.00 1725 f10b 4.75 0.5 1.0 1.5 2.0 5.25 v in = 36v v in = 72v v in = 48v i load (a) 0.01 60 efficiency (%) 70 80 90 0.1 1 10 1725 f10c 50 40 30 20 v in = 48v without r11 preload with r11 preload application regulation application efficiency
23 LT1725 typical applicatio s u 48v to isolated 5v application parts list t1: coiltronics ctx02-14989 m1: international rectifier irf620. 200v, 0.8 w n-channel mosfet d1: international rectifier 12cwq06fn. 12a, 60v schottky diode d2: bas16. 75v switching diode c1: avx tpsd156m035r0300. 15 m f, 35v tantalum capacitor c2: vishay/vitramon vj1825y155mxb. 1.5 m f, 100v, x7r ceramic capacitor c3: sanyo 6sa150m. 150 m f, 6.3v, os-con electrolytic capacitor c4: 150pf, 100v, x7r ceramic capacitor c5: 470pf, 50v, x7r ceramic capacitor c6: 1nf, 25v x7r ceramic capacitor c7: 47pf, 25v, npo ceramic capacitor c8: 0.1 m f, 25v, z5u ceramic capacitor c9: 100pf, 25v, x7r ceramic capacitor c10: 1 m f, 25v, z5u ceramic capacitor r1: 47k, 1/4w, 5% resistor r2: panasonic type erj-14rsj. 0.18 w , 1/4w, 5% resistor r3: 35.7k, 1% resistor r4: 3.01k, 1% resistor r5, r6, r7: 51k, 5% resistor r8: 2.7k, 5% resistor r9: 18 w , 5% resistor r10: 22 w , 5% resistor r11: 51 w , 1w, 5% resistor r12: 68 w , 5% resistor r13: 820k, 5% resistor r14: 33k, 5% resistor
24 LT1725 ? linear technology corporation 2000 sn1725 1725is lt/lcg 1100 4k ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments lt1424-5 isolated flyback switching regulator 5v output voltage, no optoisolator required lt1424-9 isolated flyback switching regulator 9v output , regulation maintained under light loads lt1425 isolated flyback switching regulator no third winding or optoisolator required lt1533 ultralow noise 1a switching regulator low switching harmonics and reduced emi, v in = 2.7v to 23v lt1737 high power isolated flyback controller powered from a dc supply voltage related parts dimensions in inches (millimeters) unless otherwise noted. u package descriptio s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.009 (0.229) ref 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) s16 1098 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc

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